VLSI Circuits II Lab
Text
- Lab Manual
- Quick Start Guide to Verilog [1st ed.]
Author: Brock J. LaMeres - Fundamentals of Digital Logic with Verilog Design [3rd ed.]
Authors: Stephen Brown, Zvonko Vranesic
Tools
- Questa-Intel FPGA Edition
- Xilinx Vivado
Course Rationale
In this course, students will learn a new hardware description language – Verilog. With this language, they will design various digital circuits that have been taught throughout EEE 329. They will be accustomed to new software that can compile and run Verilog modules. RTL Verilog will be thoroughly discussed in this lab. In the second part of this course, students will design simple systems using the principles learned in EEE 445.
Lab Experiments
- Review of VLSI Layout
- Verilog Constructs
- Concurrent Functionality: Operators
- Concurrent Functionality: Continuous Assignment
- Sequential Functionality: Procedural Assignment
- Sequential Functionality: Constructs: if-else, case(x/z), loops
- Sequential Circuits: D Latch & D Flipflop
- Sequential Circuits: Register
- Finite State Machine (Part 1)
- Finite State Machine (Part 2)
Marks Distribution
- Attendance (5%)
- Lab Report (10%)
- Mini-Project Presentation & Viva (25%)
- Continuous Lab Performance (30%)
- Lab Final (30%)
Mini-Project Assessment Criteria
- Presentation
- Proper Addressing of Project
- Understanding on Background, Motivation and Objectives
- Effort on Literature Review
- Usage of Methodology (Block Diagram)
- Detailed Circuit Diagram
- Usage of Figure, Graph, Table, Equation, etc.
- Key Information Delivery
- Presentation of Simulation or Hardware Prototype
- Accuracy of Presented Results and Discussion
- Presentation Skill
- Conclusion
- Report
- Proper Addressing of Project
- Introduction
- Background, Motivation and Objectives
- Literature Review
- Methodology
- Proposed Method
- Simulation or Hardware Prototype
- Result and Discussion
- Socio-economic Impact
- Environmental Impact and Sustainability
- Conclusion
- References