EEE 445

VLSI Circuits II


  1. CMOS VLSI Design: A Circuits and Systems Perspective [4th ed.]
    Authors: Neil H. E. Weste, David M. Harris
  2. Contemporary Logic Design [2nd ed.]
    Authors: Randy H. Katz, Gaetano Borriello
  3. MIT 6.111
    Introductory Digital Systems Laboratory

Course Rationale

This is a course which covers some advanced theories and techniques of digital VLSI design in CMOS technology. In this course, the students will study the advanced concepts and structures of designing digital VLSI systems include CMOS device robustness, combinational circuit design, sequential circuit design, datapath subsystems, array subsystems, finite state machines. They will also learn how to write hardware description language for any algorithm.


  • Ch. 7: Robustness [1]
    • Variability: Supply Voltage, Temperature, Process Variation, Design Corners
    • Reliability: Oxide & Interconnect Wearout, Soft Errors, Overvoltage Failure, Latchup
    • Scaling: Transistor & Interconnect Scaling, ITRS, Impacts on Design
    • Statistical Analysis of Variability: Random Variables, Sources, Impacts
  • Ch. 9: Combinational Circuit Design [1]
    • Circuit Families: Static CMOS, Ratioed Circuits, CVSL, Dynamic Circuits, Pass-Transistor Circuits
    • Circuit Pitfalls: Threshold Drops, Ratio Failures, Leakage, Charge Sharing, Power Supply Noise, Hot Spots, Minority Carrier Injection, Back-Gate Coupling, Diffusion Input Noise Sensitivity, Process Sensitivity
  • Ch. 10: Sequential Circuit Design [1]
    • Sequencing Static Circuits: Sequencing Methods, Max-Delay Constraints, Min-Delay Constraints, Time Borrowing, Clock Skew
    • Circuit Design of Latches & Flip-Flops: Conventional CMOS Latches & Flip-Flops, Pulsed Latches, Resettable & Enabled Latches & Flip-Flops, Incorporating Logic into Latches
    • Synchronizers: Metastability, Arbiters
  • Ch. 11: Datapath Subsystems [1]
    • Addition: Single-Bit Addition, CPA (RCA, Carry-Skip, CLA, Carry-Select), Multiple-Input Addition (CSA)
    • Subtraction, 1/0 Detectors, Comparators
    • Counters: Binary Counters, LFSR
    • Multiplication: Unsigned Array, Booth Encoding
  • Ch. 12: Array Subsystems [1]
    • SRAM: 6T Cells (R/W, Physical Design), Row & Column Circuitry
    • DRAM
    • ROM: Programmable, NAND, Flash
    • PLA
  • Ch. 7: Finite State Machines [2] [3]
    • Concept of SM
    • Design Approach: Moore vs Mealy

Course Outcome

  1. Interpret different types of CMOS combinational and sequential circuit, their performance and robustness.
  2. Analyze trade-offs between speed, density, programmability, ease of design, and other variables for datapath and array subsystems.
  3. Design finite state machine and different subsystems of digital processor

Marks Distribution

  • Class Test (15%)
  • Assignment & Presentation (10%)
  • Attendance (5%)
  • Midterm Exam (30%)
  • Final Exam (40%)